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Mitsubishi Electric FX5UC-96MT/DSS FX5UC CPU Module
FX5UC-96MT/DSS
Compact connector-type FX5UC PLC CPU with 48 digital inputs and 48 source transistor outputs. 24 V DC supply, built-in Ethernet and RS-485, 82.3 mm body width.
- Availability
- In Stock
- Condition
- New Original
- SKU
- FX5UC-96MT/DSS
- Lifecycle
- Active
12 months warranty
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Technical specifications
CPU capacity, field wiring and installation requirements for FX5UC-96MT/DSS.
Base controller
- Manufacturer part number
FX5UC-96MT/DSS
- Built-in I/O
48 inputs + 48 transistor outputs
- I/O connection
Connector type
- Input type
Sink/source
- Output type
Transistor source
- Engineering software
MELSOFT GX Works3
- Program capacity
64k steps; up to128k steps with supported firmware/tool
- Built-in Ethernet
10/100 Mbps, RJ45
- Built-in serial
RS-485/RS-422, up to115.2 kbps, non-isolated
Memory and expansion depend on the CPU version
Firmware1.100 and GX Works3 1.047Z or later support128k program steps and up to384 local I/O points; earlier versions use64k steps and up to256 local I/O. Local and remote I/O together remain within512 points. Memory capacity is distinct from scan time and the number of physical terminals.
Use the built-in ports for engineering and machine communication
Ethernet supports MELSOFT connections, SLMP, socket communication and MODBUS/TCP among the documented functions. The built-in serial interface supports MODBUS RTU and other listed protocols; configure protocol parameters and the terminal resistor for the connected network. Ethernet availability alone does not mean that an EtherNet/IP interface is built in.
Match the field circuit to the suffix
The /DSS version supports sink/source input wiring and supplies source-type transistor outputs. Select the input common arrangement for the sensor type; connect output loads using the source-output circuit.
Field signal and load limits
- Input signal supply
24 V DC, +20% / −15%
- Output external supply
5–30 V DC
- Y0–Y3 maximum load
0.3 A per point
- Y4 and subsequent maximum load
0.1 A per point
- Common group limit
0.8 A per common for8 output points
- Off-state output leakage
≤0.1 mA at30 V DC
- Y0–Y3 on-state drop
≤1.0 V
- Y4 onward on-state drop
≤1.5 V
Manufacturer transistor output circuits and limits
Hardware manual p.33. Use sink wiring for /D and source wiring for /DSS. Common-group and per-point limits both apply.
Fast I/O is terminal-specific
The high-speed input group is X0–X7, with200 kHz response under the specified pulse conditions. The remaining input groups have lower response frequencies. Y0–Y3 have faster switching characteristics than later outputs; do not apply the fast-channel ratings to every terminal.
Power and physical installation
- CPU supply
24 V DC, +20% / −15%
- CPU-only power consumption
11 W at24 V DC
- CPU dimensions W × H × D
82.3 ×90 ×89.1 mm
- Installation
Inside a control panel, DIN rail mounting
- General operating ambient
−20 to +55 °C, non-freezing; low-temperature and revision conditions apply
- Humidity
5–95% RH, noncondensing
Budget the complete extension system
The CPU-only wattage does not include the complete extension configuration or external field loads. The CPU’s internal supply capacities are720 mA at5 V and500 mA at24 V; calculate extension consumption and any required extension power supply for the selected modules.
Manufacturer connector-type CPU dimensions
Hardware manual p.38: use the 82.3 mm width row. The32/64/96-point bodies have different widths; leave room for I/O cables and extensions.
Manufacturer simultaneous-I/O derating curve
Hardware manual p.34. Only the lower I/O derating graph applies to these transistor CPUs; the upper relay table describes a different model.
Apply the simultaneous-ON and temperature conditions
Permitted simultaneous input/output ON ratios depend on ambient temperature and whether extension modules are connected. The -20 °C lower endpoint applies to products manufactured from June2016; earlier products have a0 °C lower endpoint. For operation below0 °C, use the manual’s low-temperature precautions. Provide external protective circuits for inductive loads and output short circuits.
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